Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study
In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show...
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Published in | Ain Shams Engineering Journal Vol. 6; no. 2; pp. 501 - 509 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
Elsevier B.V
01.06.2015
Elsevier |
Subjects | |
Online Access | Get full text |
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Summary: | In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent RON,SP/BV trade-off (BV≈400V and RON,SP=9.5mΩcm2 for Tepi=4μm and LDrift=17μm) without any added process complexity. The maximum obtained drain current is 1.8mA/μm at a gate voltage of 5V. The designed device is suitable for smart power integration. |
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ISSN: | 2090-4479 |
DOI: | 10.1016/j.asej.2014.12.003 |