Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study

In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show...

Full description

Saved in:
Bibliographic Details
Published inAin Shams Engineering Journal Vol. 6; no. 2; pp. 501 - 509
Main Authors Abouelatta-Ebrahim, Mohamed, Shaker, Ahmed, Sayah, Gihan T., Gontrand, Christian, Zekry, Abdelhalim
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.06.2015
Elsevier
Subjects
0.35 μm BiCMOS
0.35 μm BiCMOS
Breakdown voltage
nLDMOS
RESURF
Smart power integrated circuit (SPIC)
Specific ON-resistance
Smart power integrated circuit (SPIC)
Specific ON-resistance
Breakdown voltage
RESURF
0.35μm BiCMOS
nLDMOS
Online AccessGet full text

Cover

More Information
Summary:In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent RON,SP/BV trade-off (BV≈400V and RON,SP=9.5mΩcm2 for Tepi=4μm and LDrift=17μm) without any added process complexity. The maximum obtained drain current is 1.8mA/μm at a gate voltage of 5V. The designed device is suitable for smart power integration.
ISSN:2090-4479
DOI:10.1016/j.asej.2014.12.003