Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

• Published in: IEEE transactions on computers Vol. 57; no. 9; pp. 1246 - 1260
• Main Authors: Shacham, A., Bergman, K., Carloni, L.P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Chemical-mechanical polishing; chip multiprocessors; Chips; Computer simulation; Design engineering; Electronics; emerging technologies; interconnection networks; Mathematical models; Microprocessors; Networks; Photonics; chip multiprocessors; emerging technologies; interconnection networks; photonics
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2008.78

The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget. A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.