A space allocation and reuse strategy for PCM-based embedded systems

• Published in: Journal of systems architecture Vol. 60; no. 8; pp. 655 - 667
• Main Authors: Long, Linbo, Liu, Duo, Hu, Jingtong, Gu, Shouzhen, Zhuge, Qingfeng, Sha, Edwin H.-M.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.09.2014; Elsevier Sequoia S.A
• Subjects: Algorithms; Compilers; Computer memory; DRAM; Embedded systems; Endurance; Non-volatile memory; Phase change memory; Studies; Wear-leveling; Embedded systems; Phase change memory; Endurance; Non-volatile memory; Wear-leveling
• ISSN: 1383-7621; 1873-6165
• DOI: 10.1016/j.sysarc.2014.07.002

Phase change memory (PCM) has emerged as a promising candidate to replace DRAM in embedded systems, due to its appealing properties, such as zero leakage power, scalability, shock-resistivity and high density. However, it can only sustain a limited number of write operations. On the other hand, as a program in embedded systems usually distributes write traffic in an extremely unbalanced way, which could further decrease PCM lifetime. In this paper, we propose a space-based wear leveling technique in software compiler level by exploiting the program-specific features. The basic idea is to extend frequently written variables into specific-sized arrays, and evenly distribute writes on allocated array. In such way, we can effectively distribute the write traffic of the program across the whole PCM chip. A space allocation and reuse (SAR) strategy and a polynomial-time algorithm are proposed to produce optimal and near-optimal space allocation, respectively, for achieving a balanced write distribution. The experimental results show our technique can greatly extend the lifetime of PCM-based embedded systems compared with the previous work, and achieve approximately 94% the theoretical maximum of lifetime. Compared with a baseline scheme without wear-leveling mechanism, our technique introduces no more than 0.8% extra writes and 0.7% running overhead.