Vertical WS2/SnS2 van der Waals Heterostructure for Tunneling Transistors

• Published in: Scientific reports Vol. 8; no. 1; pp. 1 - 9
• Main Authors: Wang, Jiaxin, Jia, Rundong, Huang, Qianqian, Pan, Chen, Zhu, Jiadi, Wang, Huimin, Chen, Cheng, Zhang, Yawen, Yang, Yuchao, Song, Haisheng, Miao, Feng, Huang, Ru
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group 10.12.2018; Nature Publishing Group UK
• Subjects: Electric properties; Interfaces; Transistors
• ISSN: 2045-2322; 2045-2322
• DOI: 10.1038/s41598-018-35661-4

Van der Waals heterostructures composed of two-dimensional (2D) transition metal dichalcogenides (TMD) materials have stimulated tremendous research interest in various device applications, especially in energy-efficient future-generation electronics. Such ultra-thin stacks as tunnel junction theoretically present unprecedented possibilities of tunable relative band alignment and pristine interfaces, which enable significant performance enhancement for steep-slope tunneling transistors. In this work, the optimal 2D-2D heterostructure for tunneling transistors is presented and elaborately engineered, taking into consideration both electric properties and material stability. The key challenges, including band alignment and metal-to-2D semiconductor contact resistances, are optimized separately for integration. By using a new dry transfer technique for the vertical stack, the selected WS2/SnS2 heterostructure-based tunneling transistor is fabricated for the first time, and exhibits superior performance with comparable on-state current and steeper subthreshold slope than conventional FET, as well as on-off current ratio over 106 which is among the highest value of 2D-2D tunneling transistors. A visible negative differential resistance feature is also observed. This work shows the great potential of 2D layered semiconductors for new heterostructure devices and can guide possible development of energy-efficient future-generation electronics.