Nanopore-application CMOS potentiostat design with input parasitic compensation
A low-noise area-efficient potentiostat design for nanopore applications is presented. By adopting a cascode amplifier and a Wilson current mirror, the input resistance is drastically decreased, which enables one to obtain a desirable bandwidth to detect DNA translocation events in nanopore sensors....
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Published in | Electronics letters Vol. 50; no. 8; pp. 578 - 579 |
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Main Authors | , |
Format | Journal Article |
Language | English |
Published |
Stevenage
The Institution of Engineering and Technology
10.04.2014
Institution of Engineering and Technology John Wiley & Sons, Inc |
Subjects | |
Online Access | Get full text |
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Summary: | A low-noise area-efficient potentiostat design for nanopore applications is presented. By adopting a cascode amplifier and a Wilson current mirror, the input resistance is drastically decreased, which enables one to obtain a desirable bandwidth to detect DNA translocation events in nanopore sensors. A novel compensation technique is also proposed to relieve a deleterious effect by the input parasitic capacitances. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0013-5194 1350-911X 1350-911X |
DOI: | 10.1049/el.2014.0049 |