Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

• Published in: Nature communications Vol. 15; no. 1; p. 4098
• Main Authors: Daniel, John, Sun, Zheng, Zhang, Xuejian, Tan, Yuanqiu, Dilley, Neil, Chen, Zhihong, Appenzeller, Joerg
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 15.05.2024; Nature Publishing Group; Nature Portfolio
• Subjects: 142/126; 147/135; 639/925/927/1007; 639/925/927/1062; Bayesian analysis; CMOS; Computation; Controllability; Field effect transistors; Humanities and Social Sciences; Logic; Metal oxides; Molybdenum disulfide; multidisciplinary; Probability theory; Science; Science (multidisciplinary); Semiconductor devices; Semiconductors; Statistical inference; Stochasticity; Transistor circuits; Transistors; Tunnel junctions
• ISSN: 2041-1723; 2041-1723
• DOI: 10.1038/s41467-024-48152-0

Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS 2 field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint. Probabilistic bits (p-bits) are the base units of probabilistic computing, a computing scheme offering a more efficient approach than conventional binary logic in various applications. Here, the authors report the realization of a p-bit core device by combining stochastic magnetic tunnel junctions and 2D MoS 2 transistors on the same chip.