A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

• Published in: IEEE journal of solid-state circuits Vol. 35; no. 2; pp. 240 - 247
• Main Authors: Dudek, P., Szczepanski, S., Hatfield, J.V.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit testing; Circuits; CMOS; CMOS integrated circuits; CMOS process; Converters; Delay; Delay effects; Delay lines; Digital; Dynamic link libraries; Particle measurements; Position measurement; Radiation detectors; Signal resolution; Time measurement
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.823449

This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.