An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

• Published in: IEEE journal of solid-state circuits Vol. 35; no. 4; pp. 490 - 502
• Main Author: Vaucher, C.S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive systems; Architecture; Bandwidth; Circuit optimization; Circuits; Filters; Frequency; Noise; Phase locked loops; Phase noise; Purity; Settling; Signal design; Signal to noise ratio; Spectra; Tuning
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.839909

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.