A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 62; no. 1; pp. 70 - 79
• Main Authors: Lin, Jin-Yi, Hsieh, Chih-Cheng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Capacitors; Circuits; CMOS; Electric potential; Linearity; Logic; Low power; low voltage; Merging; Noise; Noise levels; SAR ADC; Switches; Switching; Switching circuits; Synthetic aperture radar; Voltage
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2014.2349571

This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage (Vcm) and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 mm 2 . With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step.