Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

• Published in: IEEE transactions on electron devices Vol. 56; no. 11; pp. 2752 - 2761
• Main Authors: Khatami, Y., Banerjee, K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Band-to-band (B2B) tunneling; Channels; Delay; Devices; Digital circuits; energy-efficient device; Gates (circuits); Inverters; Junctions; Logic gates; low power (LP); Photonic band gap; Semiconductors; Silicon germanium; sub-kT/q device; subthreshold swing; Swing; Threshold voltage; tunnel field-effect transistor (T-FET); Tunneling
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2009.2030831

In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low off currents on the order of 1 fA/mum and engineered to exhibit substantially higher on currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of ~10 4 is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.