A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 61; no. 9; pp. 2738 - 2746
• Main Authors: Cheng, Chung-Chao, Yang, Jeng-Da, Lee, Huang-Chang, Yang, Chia-Hsiang, Ueng, Yeong-Luh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Codes; Comparators; Complexity theory; Decoders; Decoding; Error correcting codes; Hardware; High-throughput decoder; low-density parity-check (LDPC) codes; min-sum algorithm; Networks; Parity check codes; Probabilistic logic; Probabilistic methods; Probability theory; Routing; Signal to noise ratio; Throughput
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2014.2312479

This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz , achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.