Utilizing Process Variations for Reference Generation in a Flash ADC

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 56; no. 5; pp. 364 - 368
• Main Authors: Sundstrom, T., Alvandpour, A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-digital conversion; Calibration; Circuits; CMOS; CMOS process; CMOS technology; Comparators; Electric potential; Flash analog-to-digital converter (ADC); High speed; high-performance design; Nanocomposites; Nanomaterials; Nanostructure; parameter variation; Power dissipation; Redundancy; TECHNOLOGY; TEKNIKVETENSKAP; Threshold voltage; Very large scale integration; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2009.2019165

This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.