Performance Analysis of 60-nm Gate-Length III-V InGaAs HEMTs: Simulations Versus Experiments
An analysis of recent experimental data for high-performance In 0.7 Ga 0.3 As high electron mobility transistors (HEMTs) for logic applications is presented. By using a fully quantum mechanical ballistic model, we simulate In 0.7 Ga 0.3 As HEMTs with gate lengths of L G = 60, 85, and 135 nm and comp...
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Published in | IEEE transactions on electron devices Vol. 56; no. 7; pp. 1377 - 1387 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.07.2009
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | An analysis of recent experimental data for high-performance In 0.7 Ga 0.3 As high electron mobility transistors (HEMTs) for logic applications is presented. By using a fully quantum mechanical ballistic model, we simulate In 0.7 Ga 0.3 As HEMTs with gate lengths of L G = 60, 85, and 135 nm and compare the result to the measured IV characteristics, including drain-induced barrier lowering, subthreshold swing, and threshold voltage variation with gate insulator (wide-bandgap barrier layer) thickness, as well as on-current performance. To first order, devices with three different oxide thicknesses and channel lengths can all be described by a ballistic model for the channel with appropriate values of parasitic series resistance. For high gate and drain voltages ( V GS -V T =0.5 V and V DS =0.5 V), however, the ballistic simulations consistently overestimate the measured on-current (a sign of higher transconductance), and they do not show the experimentally observed decrease in on-current with increasing gate length. With no parasitic series resistance at all, the simulated on-current of the L G = 60 nm device is about twice the measured current. According to the simulation, the estimated ballistic carrier injection velocity for this device is about 2.7 times 10 7 cm/s. Because of the importance of the semiconductor capacitance, the simulated gate capacitance is about 2.5 times less than the insulator/barrier capacitance. Possible causes of the transconductance degradation observed experimentally under high gate voltages in these devices are also explored. In addition to a possible gate-voltage-dependent scattering mechanism, the limited ability of the source to supply carriers to the channel and the effect of nonparabolicity are likely to play a role. The drop in the on-current at higher gate biases with increasing gate length, is an indication that the devices operate below the ballistic limit. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2009.2021437 |