A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 23; no. 5; pp. 678 - 693
• Main Authors: Daniel, L., Ong Chin Siong, Chay, L.S., Kwok Hong Lee, White, J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Buses (vehicles); Capacitance; Capacitors; Delay; Design engineering; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit synthesis; Integrated circuits; Mathematical models; Predictive models; Solid modeling; Testing; Wire
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2004.826583

In this paper, we describe an approach for generating accurate geometrically parameterized integrated circuit interconnect models that are efficient enough for use in interconnect synthesis. The model-generation approach presented is automatic, and is based on a multiparameter moment matching model-reduction algorithm. A moment-matching theorem proof for the algorithm is derived, as well as a complexity analysis for the model-order growth. The effectiveness of the technique is tested using a capacitance extraction example, where the plate spacing is considered as the geometric parameter, and a multiline bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict capacitance values for the capacitor example, and both delay and cross-talk effects over a reasonably wide range of spacing and width variation for the multiline bus example.