Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 56; no. 3; pp. 509 - 518
• Main Authors: Sundstrom, T., Murmann, B., Svensson, C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; Analog-digital conversion; Architecture; CMOS analog integrated circuits; CMOS technology; Constraining; Converters; Devices; Digital systems; Error correction; Estimates; High speed; High-speed electronics; Pipelines; Power demand; Power dissipation; Sampling methods; TECHNOLOGY; TEKNIKVETENSKAP
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2008.2002548

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.