Investigation of short-circuit failure mechanisms of SiC MOSFETs by varying DC bus voltage

• Published in: Japanese Journal of Applied Physics Vol. 57; no. 7; pp. 74102 - 74111
• Main Authors: Namai, Masaki, An, Junjie, Yano, Hiroshi, Iwamuro, Noriyuki
• Format: Journal Article
• Language: English
• Published: Tokyo The Japan Society of Applied Physics 01.07.2018; Japanese Journal of Applied Physics
• Subjects: Data buses; Electric potential; Extreme values; Failure mechanisms; Failure modes; Insulated gate bipolar transistors; Lattice vibration; MOSFETs; Numerical analysis; Robustness (mathematics); Semiconductor devices; Short circuits; Silicon; Thermal runaway
• ISSN: 0021-4922; 1347-4065
• DOI: 10.7567/JJAP.57.074102

In this study, the experimental evaluation and numerical analysis of short-circuit mechanisms of 1200 V SiC planar and trench MOSFETs were conducted at various DC bus voltages from 400 to 800 V. Investigation of the impact of DC bus voltage on short-circuit capability yielded results that are extremely useful for many existing power electronics applications. Three failure mechanisms were identified in this study: thermal runaway, MOS channel current following device turn-off, and rupture of the gate oxide layer (gate oxide layer damage). The SiC MOSFETs experienced lattice temperatures exceeding 1000 K during the short-circuit transient; as Si insulated gate bipolar transistors (IGBTs) are not typically subject to such temperatures, the MOSFETs experienced distinct failure modes, and the mode experienced was significantly influenced by the DC bus voltage. In conclusion, suggestions regarding the SiC MOSFET design and operation methods that would enhance device robustness are proposed.