Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 16; no. 1; pp. 98 - 107
• Main Authors: Pomeranz, I., Reddy, S.M.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.01.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Circuits; Cities and towns; Computer simulation; Delay; Delay defects; Delay effects; Delay lines; Design. Technologies. Operation analysis. Testing; Electrical fault detection; Electronics; Exact sciences and technology; Fault detection; fault simulation; Faults; Integrated circuits; Mathematical models; path delay faults; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; test generation; transition faults; Very large scale integration; Delay defects; Integrated circuit testing; Fault simulation; Test method; Delay time; transition faults; Reliability; path delay faults; Test generation
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2007.909796

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.