A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC

• Published in: IEEE transactions on circuits and systems for video technology Vol. 18; no. 7; pp. 949 - 960
• Main Author: Pastuszak, G.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Arithmetic; Automatic voltage control; Circuit properties; Coding, codes; Computational complexity; Computer architecture; Costs; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Encoding; Exact sciences and technology; FPGA; H.264/AVC; Hardware; Image processing; Imaging devices; Information, signal and communications theory; Logic; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Signal convertors; Signal processing; Studies; Telecommunications and information theory; Video compression; Video sharing; VLSI architecture; VLSI architecture; video compression; entropy coding; H.264/AVC; FPGA; Video coding; Performance evaluation; Image processing; High definition television; Data compression; Information rate; Implementation; Video signal processing; Image coding; VHDL language; Pricing; Variable length code; High performance; VLSI circuit; Coding circuit; Image compression; Field programmable gate array; Computational complexity; Information transmission; Binary coding; Adaptive coding; Circuit architecture; Integrated circuit; Arithmetic code; Production cost
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2008.920743

H.264/AVC offers critical advantages over other video compression schemes at the price of increased computational complexity. The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binary coder, which is the last stage of the video coder. The module conforms to H.264/AVC High Profile and supports two binary coding modes: context adaptive binary arithmetic coding (CABAC) and context adaptive variable-length coding (CAVLC). The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. Five versions of the arithmetic coding path are developed to study the area/performance tradeoff related to parallel symbol encoding. The implementation results show that the parallel symbol encoding allows higher efficiency. The whole architecture of the binary coder is described in VHDL and synthesized for different configurations to show the implementation cost of some coding options. For both CAVLC and CABAC modes, the architecture achieves the similar throughput able to support HDTV in real time.