A Fast Algorithm and Its VLSI Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding

• Published in: IEEE transactions on circuits and systems for video technology Vol. 17; no. 5; pp. 578 - 583
• Main Authors: WANG, Yu-Jen, CHENG, Chao-Chung, CHANG, Tian-Sheuan
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.05.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Architecture; Automatic voltage control; Bit rate; Computer programs; Cost engineering; Costs; Degradation; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; H.264/AVC; Image processing; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); Motion estimation; MPEG 4 Standard; Noise levels; PSNR; Quantization; Sampling, quantization; Searching; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Signal processing; Telecommunications and information theory; Very large scale integration; Video coding; Video coding; Signal compression; VLSI circuit; Processor; Motion estimation; Image processing; Information rate; Quantum effect; H.264/AVC; Computational complexity; Information transmission; Video signal processing; Circuit architecture; Degradation; Signal quantization; Integrated circuit; Signal processing; Software; Fast algorithm; Damaging; Signal to noise ratio
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2007.894050

This paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14% of searching time when compared with the previous design