Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

• Published in: IEEE electron device letters Vol. 30; no. 12; pp. 1377 - 1379
• Main Authors: Collaert, N., Aoulaiche, M., Rakowski, M., Redolfi, A., De Wachter, B., Van Houdt, J., Jurczak, M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bias; Bulk FinFET; Capacitors; Design. Technologies. Operation analysis. Testing; Devices; Doping; Dynamic random access memory; Electronics; Electrons; Exact sciences and technology; FinFETs; Integrated circuits; Integrated circuits by function (including memories and processors); one-transistor (1T) capacitorless DRAM; Optimization; Potential well; Programming; Random access memory; Read-write memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicidation; Silicon on insulator technology; Transistors; Capacitor less circuit; Bulk FinFET; MOSFET; Random access memory; Doping; Retention factor; Dual gate transistor; Readout electronics; Optimization; Self aligned technology; Non volatile memory; Integrated circuit; one-transistor (IT) capacitorless DRAM; Dynamic random access memory
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2009.2034395

In this letter, we demonstrate a one-transistor capacitorless DRAM on standard bulk FinFET, using no additional processing. It is shown that, due to the use of the ground-plane doping and optimization of the READ bias conditions, no special process adjustment is required to obtain wide programming windows and long retention times, even for fin widths down to 20 nm.