AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

• Published in: IEEE transactions on electron devices Vol. 62; no. 6; pp. 1870 - 1878
• Main Authors: Shu Yang, Shenghou Liu, Yunyou Lu, Cheng Liu, Chen, Kevin J.
• Format: Journal Article
• Language: English
• Published: IEEE 01.06.2015
• Subjects: AlGaN/GaN; capacitance-voltage (C-V); Dielectrics; Electron traps; Frequency measurement; Frequency modulation; frequency/temperature dispersion; Gallium nitride; HEMTs; interface traps; Logic gates; metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs); pulse-mode current-voltage; threshold voltage instability; pulse-mode current-voltage; capacitance-voltage ( C – V ); frequency/temperature dispersion; metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs); interface traps; threshold voltage instability; AlGaN/GaN
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2015.2420690

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth.