MRAM Cell Technology for Over 500-MHz SoC

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 4; pp. 830 - 838
• Main Authors: Sakimura, N., Sugibayashi, T., Honda, T., Honjo, H., Saito, S., Suzuki, T., Ishiwata, N., Tahara, S.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.04.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuits; Clocks; CMOS; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Flash memory; Frequency; High speed; Integrated circuits; Integrated circuits by function (including memories and processors); low switching current; Magnetic and optical mass memories; Magnetic tunneling; Magnetoelectric, magnetostrictive, magnetoacoustic, magnetooptic and magnetothermal devices. Spintronics; Magnetoresistance; Magnetoresistive random access memory; Magnetoresistivity; MRAM; National electric code; nonvolatile memories; Nonvolatile memory; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Specifications; Static random access memory; Storage and reproduction of information; systems-on-chips; Writing; Magnetoresistive device; Cell structure; Static random access memory; Access time; LSI circuit; Random access memory; Transistor; System on a chip; Switching; Magnetic storage; Magnetic tunneling junction; low switching current; Embedded systems; nonvolatile memories; Integrated circuit testing; systems-on-chips; Non volatile memory; Complementary MOS technology; MRAM; Integrated circuit; High speed; SPICE
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.891665

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum 2 , which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%