Analysis of reliability and power efficiency in cascode class-E PAs

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 5; pp. 1222 - 1229
• Main Authors: Mazzanti, A., Larcher, L., Brama, R., Svelto, F.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.05.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Applied sciences; Bandwidth; Circuit properties; Circuit topology; Circuits; Class-E; CMOS; CMOS power amplifier; CMOS technology; Design engineering; Design optimization; Design. Technologies. Operation analysis. Testing; Devices; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency; Frequency ranges; Integrated circuits; Power amplifiers; Power efficiency; Prototypes; radio-frequency (RF) circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Stacking; Stress; switching amplifier; Voltage; wireless communications; Performance evaluation; wireless communications; CMOS power amplifier; Prototype; Class E; Durability; Class-E; Cascode connection; Common source; Radiofrequency; Switching; Implementation; radio-frequency (RF) circuits; Complementary MOS technology; Power amplifier; Reliability; Peak power; switching amplifier
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.872734

Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single device, improving long-term reliability. In this paper, we focus on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13-/spl mu/m CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4-2 GHz.