Correlation of Charge Buildup and Stress-Induced Leakage Current in Cerium Oxide Films Grown on Ge (100) Substrates

• Published in: IEEE transactions on electron devices Vol. 56; no. 3; pp. 399 - 407
• Main Authors: Evangelou, E.K., Rahman, M.S., Dimoulas, A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Cerium oxide; Cerium oxide (\hbox{CeO}_{2}); Cerium oxides; Charge carrier processes; charge trapping; Construction; Current measurement; Deposition; Dielectric, amorphous and glass solid devices; Dielectrics; Electronics; Exact sciences and technology; Germanium; Germanium (Ge); Leakage current; Logic gates; Metal oxide semiconductors; rare earth oxide (REO); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Silicon substrates; Stress; stress-induced leakage current (SILC); Temperature measurement; MOS technology; Stress concentration; Cerium oxide (CeO; Electric stress; ); stress-induced leakage current (SILC); MOS capacitor; Charge carrier trapping; Relaxation; Molecular beam condensation; n type semiconductor; Stress effects; Leakage current; High k dielectric; Reliability; rare earth oxide (REO); Gates; Comparative study; Germanium (Ge); charge trapping
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2008.2011935

High-kappa films are currently deposited on Ge substrates to compensate the mobility loss, as Ge offers higher mobility compared with that of silicon. This paper deals with the reliability characteristics of cerium oxide films grown by molecular beam deposition on n-type Ge (100) substrates. MOS capacitors with Pt gate electrodes were subjected to constant voltage stress conditions at accumulation. The correlation of the charge-trapping characteristics and the stress-induced leakage current (SILC) to the applied field is observed and analyzed. The results suggest that one major problem for the potential use of rare earth oxides in future MOS technology is the existence of relaxation effects. The cross-sectional value of the bulk oxide traps is on the order of 10 -18 cm 2 , thus indicating neutral defects. Direct comparison to reported results on high- kappa/Si and SiO 2 /Si structures shows that SILC properties are related to the quality of the dielectric layers; the semiconductor substrate is immaterial.