Theoretical Study of Some Physical Aspects of Electronic Transport in nMOSFETs at the 10-nm Gate-Length

• Published in: IEEE transactions on electron devices Vol. 54; no. 9; pp. 2116 - 2136
• Main Authors: Fischetti, M.V., O'Regan, T.P., Sudarshan Narayanan, Sachs, C., Seonghoon Jin, Jiseok Kim, Yan Zhang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Collisions; Devices; Disk operating system (DOS); Electron mobility; Electronics; High- kappa gate dielectric; Insulators; Leakage current; Logic gates; low-field mobility; Materials; Monte Carlo; MOSFETs; Performance evaluation; scaling; Scattering; short channel; Silicon; surface optical phonons; transconductance; Transport
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2007.902722

We discuss selected aspects of the physics of electronic transport in nMOSFETs at the 10-nm scale: Long-range Coulomb interactions, which may degrade performance and even prevent ballistic transport from occurring; scattering with high-k insulator interfacial modes, which depresses the electron mobility but is found to affect minimally the saturated transconductance of 15-nm devices; and the use of high-mobility small effective-mass substrates, which poses serious concerns related to performance limitations due to the density-of-states (DOS) bottleneck and to the band-to-band (Zener) leakage current. On the basis of our results, we argue that ballistic transport may not only be unachievable (because of unavoidable electron-electron collisions) but may also be undesirable, as it may enhance the DOS bottleneck. We also argue that the knowledge of low-field mobility is of little use in predicting quantitatively the performance of devices in the saturated region.