Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High ( \sim1.5 GPa) Channel Stress

• Published in: IEEE electron device letters Vol. 28; no. 1; pp. 58 - 61
• Main Authors: Suthram, S., Ziegert, J.C., Nishida, T., Thompson, S.E.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bending; Calibration; Channels; Degradation; Devices; Drains; Electronics; Exact sciences and technology; Mechanical variables measurement; MOSFETs; Piezoresistance; Piezoresistive devices; Predictive models; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; strained-silicon; Stress measurement; Stresses; Tensile stress; Transistors; uniaxial; wafer bending; MOSFET; Tensile stress; strained-silicon; Electric stress; Drain current; wafer bending; Series resistance; NMOS technology; Wafer; Piezoresistance; Damaging; uniaxial
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2006.887939

A flexure-based four-point mechanical wafer bending setup is used to apply large uniaxial tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to ~700 MPa of process-induced stress. This provides the highest uniaxial channel stress to date at ~1.5 GPa. The stress altered drain-current is measured for long and short (50-140 nm) devices and the extracted pi-coefficients are observed to be approximately constant for stresses up to ~1.5 GPa. For short devices, this trend is seen only after correcting for the significant degradation in the pi-coefficients observed due to parasitic source/drain series resistances (R s d/)