A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

• Published in: IEEE journal of solid-state circuits Vol. 50; no. 4; pp. 882 - 895
• Main Authors: Nandwana, Romesh Kumar, Anand, Tejasvi, Saxena, Saurabh, Kim, Seong-Joong, Talegaonkar, Mrunmay, Elkholy, Ahmed, Choi, Woo-Seok, Elshazly, Amr, Hanumolu, Pavan Kumar
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.2015
• Subjects: Bandwidth; Calibration-free; Clocks; delta-sigma modulator; fractional-N PLL; frequency synthesizer; Interpolation; multiplying delay-locked loop (MDLL); phase interpolator (PI); Phase locked loops; Phase noise; phase-locked loop (PLL); Quantization (signal); quantization error cancellation; ring-VCO; Voltage-controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2385756

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of -104 dBc/Hz and 1.5 ps rms integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of -225.8 dB.