A logic nanotechnology featuring strained-silicon

• Published in: IEEE electron device letters Vol. 25; no. 4; pp. 191 - 193
• Main Authors: Thompson, S.E., Armstrong, M., Auth, C., Cea, S., Chau, R., Glass, G., Hoffman, T., Klaus, J., Zhiyong Ma, Mcintyre, B., Murthy, A., Obradovic, B., Shifren, L., Sivakumar, S., Tyagi, S., Ghani, T., Mistry, K., Bohr, M., El-Mansy, Y.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitive sensors; Electric fields; Electron mobility; FETs; Logic; MOSFETs; Nanostructure; Nanotechnology; Semiconductor devices; Silicon; Strain; Strain control; Transistors; Uniaxial strain
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2004.825195

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.