CMOS fully integrated reconfigurable power amplifier with efficiency enhancement for LTE applications

• Published in: Electronics letters Vol. 51; no. 2; pp. 181 - 183
• Main Authors: Tuffery, A, Deltimple, N, Kerhervé, E, Knopik, V, Cathelin, P
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 22.01.2015; IET
• Subjects: Architecture; Bias; CMOS; CMOS fully integrated reconfigurable power amplifier; CMOS integrated circuits; combiner; DC bias feed; distributed active transformer; efficiency enhancement; Engineering Sciences; frequency 2.5 GHz; high power back‐off; impedance convertors; Long Term Evolution; Low level; LTE application; Micro and nanotechnologies; Microelectronics; parallelised power cell; Partitions; Power amplifiers; power cell switching technique; size 65 nm; splitter; Switching; Transformers; Wireless communications; CMOS fully integrated reconfigurable power amplifier; size 65 nm; frequency 2.5 GHz; splitter; combiner; impedance convertors; parallelised power cell; power cell switching technique; high power back-off; distributed active transformer; DC bias feed; efficiency enhancement; power amplifiers; CMOS integrated circuits; Long Term Evolution; LTE application
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2014.3525

A fully integrated power amplifier using a power cell switching technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers are used as the splitter, the combiner and the DC bias feed to partition the power requirements among the parallelised power cells. An individual cell can be dynamically turned ON/OFF according to the desired output power. At 2.5 GHz, the measured maximum output power is 28.2 dBm and the power-added efficiency is improved for low level, +3.2 and +4.9% for 18 and 23.7 dBm, respectively.