A three-dimensional stacked fin-CMOS technology for high-density ULSI circuits

• Published in: IEEE transactions on electron devices Vol. 52; no. 9; pp. 1998 - 2003
• Main Authors: Xusheng Wu, Chan, P.C.H., Shengdong Zhang, Chuguang Feng, Chan, M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit topology; Circuits; CMOS; CMOS integrated circuits; CMOSFET; Design. Technologies. Operation analysis. Testing; Devices; Double layer; Electronics; Exact sciences and technology; FinFET; Implants; Integrated circuits; Inverters; Joints; Layout; Masks; MOSFETs; Oxides; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon films; Silicon on insulator technology; silicon-on-insulator (SOI); SRAM chips; three-dimensional integrated circuits (3-D IC); Transistors; Ultra-large-scale integration; MOSFET; CMOSFET; Scalability; Oxide layer; High density; FinFET; three-dimensional integrated circuits (3-D IC); Dual gate transistor; Two dimensional model; silicon-on-insulator (SOI); Self aligned technology; Wiring; Silicon on insulator technology; ULSI circuit; Three dimensional model; Three dimensional structure; Complementary MOS technology; Integrated circuit; Active component; Double layers; Wafer; Planar technology
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2005.854267

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.