Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

• Published in: IEEE transactions on electron devices Vol. 52; no. 4; pp. 492 - 499
• Main Authors: Akil, N., van Duuren, M., Slotboom, M., Baks, W., Goarin, P., van Schaijk, R., Tello, P.G., Cuppens, R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.04.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit optimization; CMOS; CMOS integrated circuits; Design. Technologies. Operation analysis. Testing; Devices; EEPROM; Electric potential; Electronics; EPROM; Exact sciences and technology; Gates; halo; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage currents; Magnetic and optical mass memories; Optimization; Oxides; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; source-side injection; Storage and reproduction of information; technology computer-aided design (TCAD); Transistors; Voltage; Performance evaluation; Memory devices; Gate voltage; technology computer-aided design (TCAD); Circuit design; Transistor gate; Doping profile; halo; Optimization; EEPROM; Low voltage; EEPROM memory; Non volatile memory; Gate oxide; Complementary MOS technology; Integrated circuit; Leakage current; source-side injection; Computer aided design
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2005.844760

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.