Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

• Published in: Journal of micromechanics and microengineering Vol. 17; no. 6; pp. 1200 - 1205
• Main Authors: Lin, Chiung-Wen, Yang, Hsueh-An, Wang, Wei Chung, Fang, Weileun
• Format: Journal Article
• Language: English
• Published: Bristol IOP Publishing 01.06.2007; Institute of Physics
• Subjects: Applied sciences; Exact sciences and technology; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Mechanical engineering. Machine design; Mechanical instruments, equipment and techniques; Micromechanical devices and systems; Physics; Precision engineering, watch making; Encapsulation; Wafer bonding; Electrical signal; Hermetic sealing; Anodic bonding; Surface mount technology; Silicon-on-insulator; Electrodeposition; Laser beam machining; Pyrex; Microelectromechanical device
• ISSN: 0960-1317; 1361-6439
• DOI: 10.1088/0960-1317/17/6/014

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.