A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis

• Published in: IEEE transactions on advanced packaging Vol. 27; no. 1; pp. 71 - 78
• Main Authors: Elfadel, I.M., Deutsch, A., Smith, H.H., Rubin, B.J., Kopcsay, G.V.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NY IEEE 01.02.2004; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; CMOS; CMOS process; CMOS technology; Design automation; Design methodology; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Extraction; Frequency; Impedance; Inductance; Integrated circuits; Mathematical models; Metal oxide semiconductors; Methodology; Multiconductor transmission lines; Parameter extraction; Production; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transmission lines; Frequency dependence; Circuit design; frequency-dependent multiconductor transmission lines; Multiconductor line; Modeling; Parameter extraction; Inductance; CMOS; on-chip interconnect modeling; Transmission line; CAD tool; Interconnection; Complementary MOS technology; Integrated circuit; Impedance; Computer aided design
• ISSN: 1521-3323; 1557-9980
• DOI: 10.1109/TADVP.2004.825478

This paper describes a methodology for global on-chip interconnect modeling and analysis using frequency-dependent multiconductor transmission lines. The methodology allows designers to contain the complexity of series impedance computation by transforming the generic inductance and resistance extraction problem into one of per-unit-length parameter extraction. This methodology has been embodied in a CAD tool that is now in production use by interconnect designers and complementary metal oxide semiconductor (CMOS) process technologists.