Warp Processing: Dynamic Translation of Binaries to FPGA Circuits

Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new architecture and set of dynamic CAD tools demons...

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Bibliographic Details
Published inComputer (Long Beach, Calif.) Vol. 41; no. 7; pp. 40 - 46
Main Authors Vahid, F., Stitt, G., Lysecky, R.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.07.2008
IEEE Computer Society
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Applied sciences
CAD
Circuit synthesis
Circuits
Clocks
Computer aided design
Computer architecture
Computer science; control theory; systems
dynamic synthesis
Dynamics
embedded systems
Exact sciences and technology
Field programmable gate arrays
FPGA
Hardware
just-in-time compilation
Kernel
Kernels
Language processing and microprogramming
Logic arrays
Logic devices
Microprocessors
Programmable logic arrays
Programming languages
reconfigurable computing
Software
Translations
Warp
warp processing
Code generation
Small series production
Customization
Field programmable gate array
Microprocessor
Binary code
Computer aided design
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Summary:Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new architecture and set of dynamic CAD tools demonstrate warp processing's potential.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9162
1558-0814
DOI:10.1109/MC.2008.240