Comments on “Dual-rail asynchronous logic multi-level implementation”

In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148–159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition...

Full description

Saved in:
Bibliographic Details
Published inIntegration (Amsterdam) Vol. 52; pp. 34 - 40
Main Author Balasubramanian, P.
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.01.2016
Subjects
Asynchronous logic
Boolean network
Decomposition
Integrated circuits
Logic
Multi-level implementation
Node
Very large scale integration
Decomposition
Boolean network
Node
Asynchronous logic
Multi-level implementation
Online AccessGet full text

Cover

More Information
Summary:In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148–159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation. •Comments on “Dual-rail asynchronous logic multi-level implementation” are provided.•Incorrect interpretation of disjoint sum-of-products (DSOP) form is clarified.•Possibility for the occurrence of deadlock condition is elucidated.•Problems with completion detection are described.•Naïve and incorrect decomposition of NAND gates in the function block is explained.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2015.08.001