Toward an Ultralow-Power Onboard Processor for Tongue Drive System

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 62; no. 2; pp. 174 - 178
• Main Authors: Viseh, Sina, Ghovanloo, Maysam, Mohsenin, Tinoosh
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.02.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Application specific integrated circuits; Engines; Field programmable gate arrays; Headsets; Microprocessors; Power consumption; Power demand; Prototypes; Sensors; Tongue; Training; Wireless communication; low power; onboard processor; personalized assistive device; wearable biomedical device; Application-specific integrated circuit (ASIC); machine learning; field-programmable gate array (FPGA)
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2014.2387683

The Tongue Drive System (TDS) is a new unobtrusive, wireless, and wearable assistive device that allows for real-time tracking of the voluntary tongue motion in the oral space for communication, control, and navigation applications. The latest TDS prototype appears as a wireless headphone and has been tested in human subject trials. However, the robustness of the external TDS (eTDS) in real-life outdoor conditions may not meet safety regulations because of the limited mechanical stability of the headset. The intraoral TDS (iTDS), which is in the shape of a dental retainer, firmly clasps to the upper teeth and resists sensor misplacement. However, the iTDS has more restrictions on its dimensions, limiting the battery size and consequently requiring a considerable reduction in its power consumption to operate over an extended period of two days on a single charge. In this brief, we propose an ultralow-power local processor for the TDS that performs all signal processing on the transmitter side, following the sensors. Assuming the TDS user on average issuing one command/s, implementing the computational engine reduces the data volume that needs to be wirelessly transmitted to a PC or smartphone by a factor of 1500×, from 12 kb/s to ~8 b/s. The proposed design is implemented on an ultralow-power IGLOO nano field-programmable gate array (FPGA) and is tested on AGLN250 prototype board. According to our post-place-and-route results, implementing the engine on the FPGA significantly drops the required data transmission, while an application-specific integrated circuit (ASIC) implementation in a 65-nm CMOS results in a 15× power saving compared to the FPGA solution and occupies a 0.02-mm 2 footprint. As a result, the power consumption and size of the iTDS will be significantly reduced through the use of a much smaller rechargeable battery. Moreover, the system can operate longer following every recharge, improving the iTDS usability.