Mapping application-specific topology to mesh topology with reconfigurable switches

• Published in: Chronic diseases and translational medicine Vol. 14; no. 1; pp. 9 - 16
• Main Authors: Kullu, Pinar, Ar, Yilmaz, Tosun, Suleyman, Ozdemir, Suat
• Format: Journal Article
• Language: English
• Published: Beijing The Institution of Engineering and Technology 01.01.2020; John Wiley & Sons, Inc
• Subjects: Algorithms; chip area; communicating nodes; Communication; Design; Energy consumption; Fault tolerance; fault‐tolerance capabilities; genetic algorithm; genetic algorithms; Heuristic; irregular NoC topologies; Linear programming; low‐power electronics; mapping application‐specific topology; mesh topology; Methods; network routing; network topology; network‐on‐chip; network‐on‐chip architecture; reconfigurable switches; regular NoC topologies; Research Article; routing path; two‐step method; mapping application-specific topology; network-on-chip; fault tolerance; network routing; routing path; regular NoC topologies; fault-tolerance capabilities; genetic algorithms; reconfigurable switches; mesh topology; network-on-chip architecture; network topology; chip area; genetic algorithm; two-step method; irregular NoC topologies; communicating nodes; energy consumption; low-power electronics
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2018.5202

When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors’ method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.