The challenge of signal integrity in deep-submicrometer CMOS technology

• Published in: Proceedings of the IEEE Vol. 89; no. 4; pp. 556 - 573
• Main Authors: Caignet, F., Delmas-Bendhia, S., Sicard, E.
• Format: Journal Article
• Language: English
• Published: New York IEEE 2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: CMOS technology; Computer aided design; Computer simulation; Crosstalk; Delay; Design; Design automation; Design engineering; Electromagnetism; Electronics; Engineering Sciences; Integrated circuit interconnections; Integrated circuit synthesis; Integrated circuit technology; Integrated circuits; Mathematical analysis; Mathematical models; Propagation delay; Sampling; Sampling methods; Semiconductor device modeling; Signal design; Signal integrity
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/5.920583

Advances in interconnect technologies, such as the increase in the number of metal layers, stacked vias, and the reduced routing pitch, have played a key role to continuously improve integrated circuit design and operating speed. However several parasitic effects jeopardize the benefits of scale-down. Understanding and predicting interconnect behavior is vital for designing high-performance integrated circuit design. Our paper first reviews the interconnect parasitic effects and examines their impact on circuit behavior and their increase due to lithography reduction, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay. The problem of signal integrity characterization is then discussed. In our review of the different well-established measurement methodologies such as direct probing, S-parameters, e-beam sampling and on-chip sampling, we point out weaknesses, frequency ranges, drawbacks, and overall performances of these techniques. Subsequently, the on-chip sampling system is described. This features a precise line-domain characterization of the voltage waveform directly within the interconnect and shows its application in the accurate evaluation of propagation delay, crosstalk, and crosstalk-induced delay along interconnects in deep-submicrometer technology. The sensor parts are described in detail, together with signal integrity patterns and their implementation in 0.18-/spl mu/m CMOS technology. Measurements obtained with this technique are presented. In the third part, we discuss the simulation issues, describe the two- and three-dimensional interconnect modeling problems, and review the active device models applicable to deep-submicrometer technologies in order to agree on measurements and simulations. These studies result in a set of guidelines concerning the choice of interconnect models. The last part outlines the design rules to be used by designers and their implementation within computer-aided design (CAD) tools to achieve signal integrity compliance. From a 0.18-/spl mu/m technology are derived critical variables such as crosstalk tolerance margin, maximum coupling length, and the criteria for adding a signal repeater. From these, values for low-dielectric and copper interconnects have been selected.