Analysis of Phase Noise in Phase/Frequency Detectors

The phase noise of phase/frequency detectors can significantly raise the in-band phase noise of frequency synthesizers, corrupting the modulated signal. This paper analyzes the phase noise mechanisms in CMOS phase/frequency detectors and applies the results to two different topologies. It is shown t...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 60; no. 3; pp. 529 - 539
Main Authors Homayoun, A., Razavi, B.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.03.2013
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
CMOS
Detectors
Flicker noise
inverter phase noise
Inverters
Jitter
Logic gates
Mathematical analysis
Noise
Noise levels
Optimization
oscillator phase noise
PFD
Phase frequency detector
Phase noise
PLLs
Power consumption
Topology
Transistors
white noise
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Summary:The phase noise of phase/frequency detectors can significantly raise the in-band phase noise of frequency synthesizers, corrupting the modulated signal. This paper analyzes the phase noise mechanisms in CMOS phase/frequency detectors and applies the results to two different topologies. It is shown that an octave increase in the input frequency raises the phase noise by 6 dB if flicker noise is dominant and by 3 dB if white noise is dominant. An optimization methodology is also proposed that lowers the phase noise by 4 to 8 dB for a given power consumption. Simulation and analytical results agree to within 3.1 dB for the two topologies at different frequencies.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2012.2215792