A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

• Published in: IEEE journal of solid-state circuits Vol. 50; no. 2; pp. 543 - 555
• Main Authors: Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Choi, Michael, Ho-Jin Park, Seung-Tak Ryu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 2b/cycle SAR ADC; CMOS integrated circuits; Error correction; Error correction & detection; Noise; nonbinary SAR ADC; Prototypes; Redundancy; Registers; Switches
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2364833

A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with decision redundancies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuations and comparator offset variations. The proposed dynamic register and direct DAC control scheme enhance the conversion speed by minimizing logic delay in the SAR decision loop. The proposed comparator-error detection with digital error correction scheme enhances high-speed ADC performance. A prototype 7b ADC fabricated in a 45 nm CMOS process operates at a sampling rate of 1 GS/s under a 1.25 V supply while achieving a peak SNDR of 41.6 dB and maintaining an ENOB higher than 6 up to 1.3 GHz signal frequency. The FoM under a 1.25 V supply is an 80 fJ/conversion-step with a power consumption of 7.2 mW.