Low-power high-performance double-gate fully depleted SOI circuit design

• Published in: IEEE transactions on electron devices Vol. 49; no. 5; pp. 852 - 862
• Main Authors: Rongtian Zhang, Roy, K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Circuit design; Circuits; CMOS integrated circuits; Depletion; Devices; Electric potential; Leakage; Oxides
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.998595

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added back-channel leakage; and how the coupling between the front- and back-gates affects circuit reliability. Our analyses over different technology generations using the MEDICI device simulator show that DGFD SOI circuits have significant advantages in driving high output load. DGFD SOI circuits also show excellent ability in controlling leakage current. However, for low output load, no gain is obtained for DGFD SOI circuits. Also, it is necessary to optimize the back-gate oxide thickness for best leakage control. Moreover, threshold variation may cause reliability problems for thin back-gate oxide DGFD SOI circuits operated at low supply voltage.