Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

• Published in: IEEE transactions on electron devices Vol. 47; no. 4; pp. 789 - 796
• Main Authors: Mahapatra, S., Parikh, C.D., Rao, V.R., Viswanathan, C.R., Vasi, J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Channels; Charge; Charge distribution; Degradation; Devices; MOSFETs; Oxides; Spreads
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.830995

The influence of channel length and oxide thickness on the hot-carrier induced interface (N/sub it/) and oxide (N/sub ot/) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate N/sub it/ and N/sub ot/ profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N/sub it/ and N/sub ot/ profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N/sub it/ generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N/sub it/ profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.