Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing

• Published in: IEEE journal of solid-state circuits Vol. 50; no. 2; pp. 610 - 618
• Main Authors: Paek, Seungwook, Shin, Wongyu, Lee, Jaeyoung, Kim, Hyo-Eun, Park, Jun-Seok, Kim, Lee-Sup
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Algorithm design and analysis; area-efficient; Clocks; collaborative sensing; microprocessors; Sensors; spatial low-pass filtering effect; System-on-chip; Temperature sensors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2375335

Spatial thermal distribution of a chip is an essential information for dynamic thermal management. To get a rich thermal map, the sensor area is required to be reduced radically. However, squeezing the sensor size is about to face its physical limitation. In this background, we propose an area-efficient thermal sensing technique: hybrid temperature sensor network. The proposed sensor architecture fully exploits the spatial low-pass filtering effect of thermal systems, which implies that most of the thermal information resides in very low spatial frequency region. Our on-chip sensor network consists of a small number of accurate thermal sensors and a large number of tiny relative thermal sensors, responsible for low and high spatial frequency thermal information respectively. By combining these sensor readouts, a thermal map upsampler synthesizes a higher spatial resolution thermal map with a proposed guided upsampling algorithm.