Total-Ionizing-Dose Effects in Modern CMOS Technologies

• Published in: IEEE transactions on nuclear science Vol. 53; no. 6; pp. 3103 - 3121
• Main Author: Barnaby, H.J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 1/f noise; CMOS; CMOS technology; Design engineering; Devices; Hardness; High K dielectric materials; high-k; interface traps; Ionizing radiation; Isolation technology; Moore's Law; oxide trapped charge; Paper technology; radiation; Radiation effects; RILC; Semiconductor device noise; Semiconductor materials; Semiconductors; shallow trench isolation; Silicon on insulator technology; silicon-on-insulation (SOI); total ionizing dose
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2006.885952

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by ionizing radiation exposure have diminished by aggressive semiconductor scaling, the question remains whether there may be unknown, potentially worse threats lurking in the deep submicron regime. This manuscript provides a basic overview of some of the materials, devices, and designs that are being explored or, in some cases, used today. An overview of radiation threats and how radiation effects can be characterized is also presented. Last, the paper provides a detailed discussion of what we know now about how modern devices and materials respond to radiation and how we may assess, through the use of advanced analysis and modeling techniques, the relative hardness of future technologies