A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

• Published in: IEEE journal of solid-state circuits Vol. 50; no. 3; pp. 737 - 748
• Main Authors: Woo-Seok Choi, Anand, Tejasvi, Guanghua Shu, Elshazly, Amr, Hanumolu, Pavan Kumar
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth; Burst-mode receiver; clock and data recovery; Clocks; digital CDR; edge injection; gated VCO; Jitter; jitter tolerance; jitter transfer; Phase locked loops; Phase noise; Receivers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2390613

A full-rate burst-mode receiver that achieves fast on/off operation needed for energy-proportional links is presented. By injecting input data edges into the oscillator embedded in a classical Type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves instantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of conventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscillator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any frequency error and helps improve CDR's immunity to oscillator frequency drift during the power-on and -off states. This also improves CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90 nm CMOS process, the prototype receiver instantaneously locks onto the very first data edge and consumes 6.1 mW at 2.2 Gb/s. Owing to its short power-on time, the receiver's energy efficiency varies only from 2.77 pJ/bit to 3.87 pJ/bit when the effective data rate is varied from 0.44 Gb/s to 2.2 Gb/s. Input sensitivity of the receiver is 36 mV for a BER of 10 -12 .