Low-Power and Area-Efficient Shift Register Using Pulsed Latches

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 62; no. 6; pp. 1564 - 1571
• Main Author: Yang, Byung-Do
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: area-efficient; Clocks; Delays; flip-flop; Latches; Power demand; pulsed clock; pulsed latch; shift register; Shift registers; Transistors
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2015.2418837

This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 μm CMOS process with VDD=1.8V. The core area is 6600 μm 2 . The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops.