Using Floating-Gate Memory to Train Ideal Accuracy Neural Networks

• Published in: IEEE journal on exploratory solid-state computational devices and circuits Vol. 5; no. 1; pp. 52 - 57
• Main Authors: Agarwal, Sapan, Garland, Diana, Niroula, John, Jacobs-Gedrim, Robin B., Hsia, Alex, Van Heukelom, Michael S., Fuller, Elliot, Draper, Bruce, Marinella, Matthew J.
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.06.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog; flash; floating gate; Floating point arithmetic; Handwriting; Laboratories; Logic gates; MATHEMATICS AND COMPUTING; memristor; neural network; neural network (NN); Neural networks; neuromorphic; Nonvolatile memory; Semiconductor devices; Silicon; silicon-oxygen-nitrogen-oxygen-silicon (SONOS); SONOS; SONOS devices; Static random access memory; Training; Transistors; Weight
• ISSN: 2329-9231; 2329-9231
• DOI: 10.1109/JXCDC.2019.2902409

Floating-gate silicon-oxygen-nitrogen-oxygen-silicon (SONOS) transistors can be used to train neural networks to ideal accuracies that match those of floating-point digital weights on the MNIST handwritten digit data set when using multiple devices to represent a weight or within 1% of ideal accuracy when using a single device. This is enabled by operating devices in the subthreshold regime, where they exhibit symmetric write nonlinearities. A neural training accelerator core based on SONOS with a single device per weight would increase energy efficiency by 120×, operate 2.1× faster, and require 5× lower area than an optimized SRAM-based ASIC.