L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 16; no. 6; pp. 628 - 638
• Main Authors: Safi, E., Moshovos, A., Veneris, A.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NJ IEEE 01.06.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Applied sciences; Arrays; Circuit properties; Computer architecture; Computer simulation; Computers, microcomputers; Counting; counting bloom filters; Counting circuits; Delay; Delay estimation; Detectors; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Fabrication; Filters; Hardware; implementation; Integrated circuits; Integrated circuits by function (including memories and processors); Linear feedback shift registers; low power; Mathematical analysis; microprocessors; Organizations; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensor arrays; Studies; Testing; Theoretical study. Circuits analysis and design; Very large scale integration; Static random access memory; Processor; Circuit simulation; Random access memory; Measurement sensor; Feedback regulation; Compact design; Implementation; Shift register; counting bloom filters; Manufacturing process; Computer architecture; Integrated circuit; Analytical method; low power; Delay time; Up down counter; Microprocessor; microprocessors; Low-power electronics
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2000244

An increasing number of architectural techniques have relied on hardware counting bloom filters (CBFs) to improve upon the energy, delay, and complexity of various processor structures. CBFs improve the energy and speed of membership tests by maintaining an imprecise and compact representation of a large set to be searched. This paper studies the energy, delay, and area characteristics of two implementations for CBFs using full custom layouts in a commercial 0.13-mum fabrication technology. One implementation, S-CBF, uses an SRAM array of counts and a shared up/down counter. Our proposed implementation, L-CBF, utilizes an array of up/down linear feedback shift registers and local zero detectors. Circuit simulations show that for a 1 K-entry CBF with a 15-bit count per entry, L-CBF compared to S-CBF is 3.7times or 1.6times faster and requires 2.3times or 1.4times less energy depending on the operation. Additionally, this paper presents analytical energy and delay models for L-CBF. These models can estimate energy and delay of various CBF organizations during architectural level explorations when a physical level implementation is not available. Our results demonstrate that for a variety of L-CBF organizations, the estimations by analytical models are within 5% and 10% of Spectre simulation results for delay and energy, respectively.