Fabrication process for Josephson computer ETL-JC1 using Nb tunnel junctions

• Published in: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States) Vol. 27; no. 2; pp. 3109 - 3112
• Main Authors: Nakagawa, H., Kurosawa, I., Aoyagi, M., Takada, S.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.03.1991; Institute of Electrical and Electronics Engineers
• Subjects: 990200 > Mathematics & Computers; ALUMINIUM COMPOUNDS; ALUMINIUM OXIDES; Applied sciences; Arithmetic; BEAMS; CHALCOGENIDES; CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; CRITICAL CURRENT; CURRENTS; DATA ACQUISITION SYSTEMS; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRICAL PROPERTIES; ELECTRONIC CIRCUITS; Electronics; ELEMENTS; ETCHING; Exact sciences and technology; FABRICATION; Fluctuations; GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ION BEAMS; JOSEPHSON JUNCTIONS; JUNCTIONS; Large scale integration; LAYERS; LOGIC CIRCUITS; METALS; NIOBIUM; OXIDES; OXYGEN COMPOUNDS; PHYSICAL PROPERTIES; Registers; RELIABILITY; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; STORAGE; Superconducting devices; Superconducting films; SUPERCONDUCTING JUNCTIONS; SUPERCONDUCTIVITY; SURFACE FINISHING; Temperature; THERMAL CYCLING; TRANSITION ELEMENTS 665412 > Superconducting Devices > (1992-); TUNNEL EFFECT
• ISSN: 0018-9464; 1941-0069
• DOI: 10.1109/20.133870

The fabrication process that was used to develop a multichip Josephson computer named ETL-JC1 is described. The ETL-JC1 consists of four Josephson LSI chips: a register arithmetic logic unit chip (RALU), a sequence control unit chip (SQCU), a 1280-b read-only memory chip (IROU), and a 1-kb random access memory chip (DRAU). The fabrication process, based on a 3- mu m Nb/AlO/sub x//Nb junction technology, has been developed to make a complete set of the Josephson LSI chips. The present fabrication process includes a trilayer tunnel junction formation, a Nb underlayer method, a self-aligned insulation method, a reactive ion etching (RIE) process, an etching stopper layer formation, and a superconducting contact formation. The Josephson critical current density was controlled by the oxidation time within the fluctuation of +or-20% in the LSI fabrication runs. The resistors were made of palladium metal film on the LSI chips. The sheet resistance was controlled within the fluctuation between -12.5% and +19% in the LSI runs. It was found that the Josephson LSI chips fabricated by this process showed a high reliability for a long-term storage at room temperature and thermal cyclings between 4.2 K and room temperature without any passivation layers on the LSI surface.