Combining Topological Hardware and Topological Software: Color-Code Quantum Computing with Topological Superconductor Networks

• Published in: Physical review. X Vol. 7; no. 3; p. 031048
• Main Authors: Litinski, Daniel, Kesselring, Markus S., Eisert, Jens, von Oppen, Felix
• Format: Journal Article
• Language: English
• Published: College Park American Physical Society 15.09.2017
• Subjects: Boxes; Braiding; Color; Computer architecture; Condensed matter physics; Cooper pairs; Distillation; Elementary excitations; Error correcting codes; Error correction; Error correction & detection; Fault tolerance; Fermions; Gates; Hardware; Hexagonal cells; Information theory; Ingredients; Logic circuits; Nanowires; Networks; Quantum computers; Quantum computing; Quantum phenomena; Qubits (quantum computing); Software
• ISSN: 2160-3308; 2160-3308
• DOI: 10.1103/PhysRevX.7.031048

We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely, the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture, including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and we present protocols for realizing topologically protected Clifford gates. These hexagonal-cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome read-out and logical T gates via magic-state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and we give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but it could also be realized in alternative settings such as quantum-Hall–superconductor hybrids.